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TECHNICAL DATA
KK4024B
7 Stage Ripple-Carry Binary Counter/Divider
High-Voltage Silicon-Gate CMOS
The KK4024B is ripple-carry binary counter. All counter stages are master-slave flip-flops. The state of a counter advances one count on the negative transition of each input pulse; a high level on the RESET line resets the counter to its all zeros state. Schmitt trigger action on the inputpulse line permits unlimited rise and fall times. * Operating Voltage Range: 3.0 to 18 V * Maximum input current of 1 A at 18 V over full package-temperature range; 100 nA at 18 V and 25C * Noise margin (over full package temperature range): 1.0 V min @ 5.0 V supply 2.0 V min @ 10.0 V supply 2.5 V min @ 15.0 V supply
ORDERING INFORMATION KK4024BN Plastic KK4024BD SOIC TA = -55 to 125 C for all packages
LOGIC DIAGRAM PIN ASSIGNMENT
FUNCTION TABLE
Inputs Clock Reset L L X H Output Output state No change Advance to next state All Outputs are low
PIN 14 =VCC PIN 7 = GND PIN 8,10,13 = NO CONNECTION
X=don't care
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KK4024B
MAXIMUM RATINGS*
Symbol VCC VIN VOUT IIN PD PD Tstg TL
*
Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage (Referenced to GND) DC Output Voltage (Referenced to GND) DC Input Current, per Pin Power Dissipation in Still Air, Plastic DIP+ SOIC Package+ Power Dissipation per Output Transistor Storage Temperature Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP or SOIC Package)
Value -0.5 to +20 -0.5 to VCC +0.5 -0.5 to VCC +0.5 10 750 500 100 -65 to +150 260
Unit V V V mA mW mW C C
Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. +Derating - Plastic DIP: - 10 mW/C from 65 to 125C SOIC Package: : - 7 mW/C from 65 to 125C
RECOMMENDED OPERATING CONDITIONS
Symbol VCC VIN, VOUT TA Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage, Output Voltage (Referenced to GND) Operating Temperature, All Package Types Min 3.0 0 -55 Max 18 VCC +125 Unit V V C
This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND(VIN or VOUT)VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open.
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KK4024B
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
VCC Symbol VIH Parameter Minimum High-Level Input Voltage Maximum Low Level Input Voltage Minimum High-Level Output Voltage Maximum Low-Level Output Voltage Maximum Input Leakage Current Maximum Quiescent Supply Current (per Package) Minimum Output Low (Sink) Current Test Conditions VOUT=0.5V or VCC - 0.5V VOUT=1.0V or VCC - 1.0V VOUT=1.5V or VCC - 1.5V VOUT=0.5V or VCC - 0.5V VOUT=1.0V or VCC - 1.0V VOUT=1.5V or VCC - 1.5V VIN=GND or VCC V 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 18 5.0 10 15 20 5.0 10 15 5.0 5.0 10 15 Guaranteed Limit -55C 3.5 7 11 1.5 3 4 4.95 9.95 14.95 0.05 0.05 0.05 0.1 5 10 20 100 0.64 1.6 4.2 -2.0 -0.64 -1.6 -4.2 25C 3.5 7 11 1.5 3 4 4.95 9.95 14.95 0.05 0.05 0.05 0.1 5 10 20 100 0.51 1.3 3.4 -1.6 -0.51 -1.3 -3.4 125 C 3.5 7 11 1.5 3 4 4.95 9.95 14.95 0.05 0.05 0.05 1.0 150 300 600 3000 0.36 0.9 2.4 mA -1.15 -0.36 -0.9 -2.4 Unit V
VIL
V
VOH
V
VOL
VIN=GND or VCC
V
IIN ICC
VIN= GND or VCC VIN= GND or VCC
A A
IOL
VIN= GND or VCC UOL=0.4 V UOL=0.5 V UOL=1.5 V
mA
IOH
Minimum Output VIN= GND or VCC High (Source) Current UOH=2.5 V UOH=4.6 V UOH=9.5 V UOH=13.5 V
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KK4024B
AC ELECTRICAL CHARACTERISTICS (CL=50pF, RL=200k, Input tr=tf=20 ns)
VCC Symbol tPLH, tPHL Parameter Maximum Propagation Delay, Clock to Q1 (Figure 1) Maximum Propagation Delay, Qn to Qn+1 (Figure 3) Maximum Propagation Delay, Reset to Any Q (Figure 2) Maximum Output Transition Time (Figure 1) V 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 360 160 130 330 80 60 280 120 100 200 100 80 3.5 8 12 Guaranteed Limit -55C 25C 360 160 130 330 80 60 280 120 100 200 100 80 3.5 8 12 7.5 125C 720 320 260 660 160 120 560 240 200 400 200 160 1.75 4 6 Unit ns
tPLH, tPHL
ns
tPHL
ns
tTLH, tTHL
ns
fmax
Maximum Clock Frequency(Figure 1)
MHz
CIN
Maximum Input Capacitance
pF
TIMING REQUIREMENTS (CL=50pF, RL=200k, Input tr=tf=20 ns)
VCC Symbol tw Parameter Minimum Pulse Width, Clock (Figure 1) V 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 140 60 40 200 80 60 350 150 100 Guaranteed Limit -55C 25C 140 60 40 200 80 60 350 150 100 Unlimited 125C 280 120 80 400 160 120 700 300 200 Unit ns
tw
Minimum Pulse Width, Reset (Figure 2)
ns
trem
Minimum Removal Time, Reset(Figure 2)
ns
tr, tf
Maximum Input Rise and Fall Times, Clock (Figure 1)
s
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KK4024B
Figure 1. Switching Waveforms
Figure 2. Switching Waveforms
Figure 3. Switching Waveforms
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KK4024B
TIMING DIAGRAM
EXPANDED LOGIC DIAGRAM
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KK4024B
N SUFFIX PLASTIC DIP (MS - 001AA)
A 14 8 B 1 7
Dimensions, mm Symbol A B MIN 18.67 6.10 0.36 1.14 2.54 7.62 0 2.92 7.62 0.20 0.38 10 3.81 8.26 0.36 MAX 19.69 7.11 5.33 0.56 1.78
F
L
C D F G
J
C -T- SEATING N G D 0.25 (0.010) M T K
PLANE
M H
H J K L M N
NOTES: 1. Dimensions "A", "B" do not include mold flash or protrusions. Maximum mold flash or protrusions 0.25 mm (0.010) per side.
D SUFFIX SOIC (MS - 012AB)
A 14 8
Dimensions, mm Symbol. A MIN 8.55 3.80 1.35 0.33 0.40 1.27 5.72 0 0.10 0.19 5.80 0.25 8 0.25 0.25 6.20 0.50 MAX 8.75 4.00 1.75 0.51 1.27
H
B
P
B C D
C R x 45
1
G
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F G H
-TD 0.25 (0.010) M T C M K
SEATING PLANE
J
F
M
J K M P R
NOTES: 1.Dimensions A and B do not include mold flash or protrusion. 2.Maximum mold flash or protrusion 0.15 mm (0.006) per side for A; for B - 0.25 mm (0.010) per side.
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